1. Field of the Invention
The present invention relates to output driving circuits, and more particularly, to an output driving circuit for maintaining duty ratios of input/output signals constant.
2. Background of the Related Art
In general, a core voltage of an integrated circuit differs from an I/O voltage outside of the integrated circuit. Owing to development of technology for reducing power consumption, when the core voltage drops gradually, the outside (PCB board) power of the integrated circuit is maintained without any change. Therefore, for providing a core voltage signal to an outside of the integrated circuit, the output driving circuit is required for shifting a level of the core voltage to a voltage level outside of the integrated circuit.
The output driving circuit in general is provided with a level shifter for shifting the voltage level. However, if the level shifter shifts the voltage level of an input signal to the voltage level required at the outside of the integrated circuit, the duty ratio of the shifted signal is changed, along with the voltage level. There has been a problem in that the level shifter can not be used for an integrated circuit operative at a fast speed.
The problem of the related art will be described in more detail, with reference to the attached drawings. FIG. 1 illustrates a block diagram showing a related art output driving circuit.
Referring to FIG. 1, the related art output driving circuit is provided with a first level shifter 100 for receiving an input signal to be provided to an outside of an integrated circuit and shifting a voltage level of the input signal to a voltage level required at the outside of the integrated circuit, a second level shifter 110 for receiving an output enable signal, and shifting a voltage level of the output enable signal to a voltage level required at the outside of the integrated circuit, and an output driving unit 500 for forwarding the input signal having the voltage level shifted under the control of the output enable signal from the second level shifter 110 to the outside of the integrated circuit. The operation of the output driving circuit will be described.
The first level shifter 100 receives the input signal to be provided to the outside of the integrated circuit, and shifts the voltage level of the input signal to the voltage level required at the outside of the integrated circuit. The voltage level of the input signal generated at the integrated circuit is lower than the voltage level required at the outside of the integrated circuit. The second level shifter 110 receives an output enable signal, and shifts the voltage level of the output enable signal to the voltage level required at the outside of the integrated circuit.
The output driving unit 500 forwards the input signal having the voltage level shifted under the control of the output enable signal from the second level shifter 110 to the outside of the integrated circuit.
FIG. 2 illustrates a circuit diagram of the related art first or second level shifter.
Referring to FIG. 2, the first or second level shifter 100 or 110 is provided with a plurality of inverters INV1, and INV2 for receiving, inverting, and delaying a signal in succession, a sense amplifier 200 for amplifying the inverted and delayed signal, and a plurality of inverters INV3 and INV4 for inverting, and delaying the amplified signal in succession, and providing to the driving unit 500.
The sense amplifier 200, of a mirror type, is provided with a PMOS transistor PM1 and an NMOS transistor NM1, and a PMOS transistor PM2 and an NMOS transistor NM2 connected in series respectively between a power terminal VDD the voltage level the outside of the integrated circuit requires applied thereto, and ground.
The PMOS transistor PM1 has a gate connected to a connecting point of the PMOS transistor PM2 and the NMOS transistor NM2, and the PMOS transistor PM2 has a gate connected to a connecting point of the PMOS transistor PM1 and the NMOS transistor NM1. In this instance, the connecting point of the PMOS transistor PM2 and the NMOS transistor NM2 is an output terminal of the sense amplifier 200.
The NMOS transistor NM1 has a gate connected to receive the signal or the output enable signal through the inverters INV1 and INV2, and the NMOS transistor NM2 has a gate connected to receive the signal or the output enable signal through the inverter INV1.
The operation of the related art first or second level shifter 100 or 110 will be described.
The inverter INV1 inverts the input signal to be forwarded to the outside of the integrated circuit, or the output enable signal (for convenience of description, will be called as an input signal), and provides to the gate of the NMOS transistor NM2. Along with this, the inverter INV2 inverts the inverted input signal, and provides to the gate of the NMOS transistor NM1.
Then, since the NMOS transistor NM1, or the NM2 is turned on selectively, to turn on the PMOS transistor PM1 or PM2 selectively accordingly, the voltage level of the power terminal VDD is provided to the connecting point of the NMOS transistor NM2 and the PMOS transistor PM2. That is, an output signal of a voltage level required at the outside of the integrated circuit is generated at the connecting point of the NMOS transistor NM2 and the PMOS transistor PM2. Then, the inverter INV3 and INV4 delay the output signal, and provides to the driving unit 500.
For an example, when the input signal has a high level voltage, since the NMOS transistor NM1 and the PMOS transistor PM2 are turned on, and the NMOS transistor NM2 and the PMOS transistor PM1 are turned off, the high level voltage from the power terminal VDD is provided through the PMOS transistor PM2. Then, the high level voltage is provided to the driving unit 500 through the inverters INV3 and INV4.
Opposite to this, if the input signal has a low level voltage, since the NMOS transistor NM1 and the PMOS transistor PM2 are turned off, and the NMOS transistor NM2 and the PMOS transistor PM1 are turned on, ground level voltage is provided through the PMOS transistor PM2. Then, the ground level voltage is provided to the driving unit 500 through the inverters INV3 and INV4.
In such a related art first or second level shifter 100 or 110, because the input signal is inverted and delayed through the inverter INV1 and provided to the gate of the NMOS transistor NM2, and inverted and delayed through the inverter INV2 again and provided to the gate of the NMOS transistor INV1, the signals provided to the gate of the NMOS transistors NM1 and NM2 have different delay time periods.
Moreover, in the first or second level shifter 100 or 110, since, when the input signal has the high level voltage, the PMOS transistor PM2 is turned on to provide the power from the power terminal VDD which is a high level voltage through the PMOS transistor PM2, and when the input signal is low level voltage, the NMOS transistor NM2 is turned on to provide the ground level voltage which is the low level voltage through the NMOS transistor NM2, generating paths of the high level voltage and the low level voltage in the sense amplifier 200, being the PMOS transistor PM2 and the NMOS transistor NM2, differ from each other, and operation delay time periods of the PMOS transistor PM2 and the NMOS transistor NM2 also differ from each other.
Thus, in the first and second level shifter 100 and 110, the delay time periods of the two signals provided to the two input terminals of the sense amplifier 200 differ from each other, and delay time periods required for providing the high level voltage and the low level voltage in response to the two signals differ from each other. Therefore, when a voltage level of a signal is shifted and provided to the outside of the integrated circuit, since the duty ratio of the signal also changes, there has been a problem in that the first and second level shifter 100 and 110 can not be used in the integrated circuit operative at a fast speed.
That is, the duty ratio of a pulse signal processed in the integrated circuit is 50:50, and a cyclic period of the pulse signal is 5 ns, a high level time period and a low level time period of the pulse signal are 2.5 ns, respectively. In a case a voltage level of such a pulse signal is shifted according to the related art output driving circuit, due to a difference of the delay time period of the first and second level shifters 100 and 110, if the high level time periods of the pulse signals respectively provided to the first and second level shifters 100, and 110 differ in a range of 1 ns, the high level time period and the low level time period of the pulse signals respectively provided from the first and second level shifters 100 differ in ranges of 1.5 ns and 3.5 ns respectively, which can not be used in an integrated circuit operative at a fast speed.